The present invention relates to a method and an apparatus of fabricating a substrate having a fine circuit pattern such as semiconductor device or liquid crystal, particularly to a technology of inspecting a semiconductor device and relates to a technology of evaluating electric properties by a wafer in the midst of a procedure of fabricating a semiconductor device and an inspection technology for carrying out defect analysis on electric properties of a wafer finished with fabricating steps.
An explanation will be given of inspection of a semiconductor wafer as an example.
It is necessary that a semiconductor device stores data written to a transistor for a predetermined period of time. For such purpose, there is formed a junction on a surface of a substrate and electric charge stored in the transistor is prevented from being leaked under a condition other than predetermined potential. When leakage failure (retention failure) occurs, for example, in the case of a memory product, written data vanishes.
As a method of evaluating such a leakage failure, there is known a method of carrying out an electric test on a finished product and directly evaluating electric properties. However, even when leakage failure occurs at an initial stage of fabrication, that is, a stage of ion implantation and heat treatment for forming a junction, presence or absence of the leakage failure cannot be detected until the product is finished and the electric test is carried out.
As a method of evaluating a wafer by using electron beam at a middle stage of steps, there is a description with regard to a method of evaluating presence or absence of leakage failure by measuring substrate absorption current in Japanese Patent Laid-Open No. 326165/1994. Further, there is a description with regard to a method of inspecting an electric defect of a semiconductor circuit by utilizing potential contrast in Japanese Patent Laid-Open No. 121561/1999 and Japanese Patent Laid-Open No. 8278/1999.
Although there is the description with regard to the method of evaluating presence or absence of failure by measuring the substrate absorption current in Japanese Patent Laid-Open NO. 326165/1994, the substrate current is very weak and therefore, it is necessary to scan thereof by retarding scan speed of electron beam and the presence or absence cannot be evaluated with regard to an area of a wide range at high speed. Further, there is not a description with regard to a method of inspecting junction leakage failure at all.
Next, concerning Japanese Patent Laid-Open No. 121561/1999 and Japanese Patent Laid-Open No. 8278/1999, with regard to a transistor having a junction, although a description is given to a method of detecting opening/nonopening of a hole pattern or wiring shortage by a secondary electron amount, there is not a description with regard to a method of inspecting junction leakage failure at all.
As described in the conventional technologies, with regard to leakage failure, particularly junction leakage caused in a semiconductor device, there is only a method of electrically inspecting a chip finished with preceding steps. However, a step of ion implantation or heat treatment for forming a junction is at an initial stage of fabrication steps and therefore, even when a failure occurs at the stage, the failure cannot be detected until the wafer is finished and the electric test is carried out and a time period is required since occurrence of failure until a countermeasure thereagainst is executed.
Further, at a stage of developing a semiconductor, a failure in forming a very fine pattern is liable to cause at respective process. When such a failure occurs, leakage failure cannot be detected even by the electric test. That is, conventionally, after development of a process of forming a very fine pattern has been finished and a failure is not caused in the fabrication process, a failure at an initial stage of fabrication is detected by using a finished wafer and therefore, an enormous time period of several months level is consumed as a countermeasure thereagainst, which constitutes a factor of retarding a time period of developing a semiconductor.
Further, when the electric test is carried out, it is necessary to bring a stylus into contact with a wafer and therefore, there poses a problem that only a finished wafer can be inspected. Further, in order to bring a stylus into contact with a transistor one by one, it is necessary to use an extremely fine needle and a time period is required for touching the needle and therefore, there poses a problem that it is difficult to apply measurement on transistors one by one.
Further, according to the inspection method in which electron beam is irradiated to a transistor and a leakage amount is measured by absorption current, the absorption current amount is very weak and therefore, an enormous time period is required for measuring one location and there poses a problem that the inspection method is inappropriate for inspection for finding out a failed portion in a wide area.